1. Field of the Invention
This invention relates to a procedure for fabrication of hermetic vias which are substantially solid throughout and substantially without voids and which may include a bump or bumps on a surface or surfaces of the substrate connected by the vias.
2. Brief Description of the Prior Art
Most of the interconnect circuits built for radio frequency microwave application in 10 or 15 mils thick alumina substrates have approximately 8 mil diameter vias filled with gold. Thin film interconnect fabrication processes require solid vias (completely filled vias) to minimize multi-layer defects. During the via plating process, a gold xe2x80x9cmushroomxe2x80x9d grows external to the via. This gold mushroom growth external to the via can lead to a void within the via. The void within the via requires extensive cleaning after polishing. Further, the via void can hold the processing chemicals which can leak out during multi-layer processing, causing stains and potential adhesion defects. It is therefore apparent that initial avoidance of formation of the void would be highly beneficial in fabrication techniques.
In the fabrication of high frequency modules, such as, for example, receive/transmit modules, hermeticity of the module is an essential requirement. In order to obtain such hermeticity in accordance with the prior art, it has been necessary to encase the module within an hermetic metal housing. The inclusion of the metal housing materially increases the cost of fabrication of such modules.
There is currently no known method for fabrication of hermetic gold filled vias other than in accordance with the present invention.
In accordance with the present invention, the above described via related problem is minimized if not eliminated. When the vias are hermetic, the need for a separate metal housing to provide the required hermeticity is negated and there is provided a module which is hermetic and which does not require the auxiliary metal housing of the prior art.
Briefly, the problem of the prior art is overcome by providing a ceramic substrate which is a wall of the module, such as, for example, the bottom surface, with hermetic vias with the thin film interconnect functioning as the base plate of the module. Expensive hermetic feed throughs to the modules are eliminated by this invention whereby electrical connections to the module I/Os can be formed through the hermetic vias.
A package includes the bottom having one or more vias and metallization around the edges to connect a metal lid therein. A metal alloy lid is sealed to the edges of the substrate with hermetic vias bottom to form the completed package. All interconnects and circuitry are disposed on the interior surface of the bottom with all connection to the exterior made through the hermetic vias, it being understood that plural such vias can be disposed in the bottom.
Briefly, in accordance with a first embodiment of the present invention, the via is formed and plated using, generally, many of the procedures of the prior art. The steps involved are to provide the vias through a ceramic substrate, generally but not limited to alumina, preferably by laser drilling. A seed metal to which the plating material will be later used will adhere, which includes but is not limited to TiW, Ni, Cr, Ta, Ti and W, is then deposited, preferably by sputtering, over preferably one and possibly both major opposing surfaces of the substrate which will be connected together by the via and the seed metal is then covered with a dry film resist. The substrate is then properly aligned and the resist is exposed through a mask which patterns the regions of the resist to be exposed. The resist is then exposed through the mask and developed to leave seed metal and resist on one or both major surface with the via being exposed. The substrate is then placed in an electroplating, generally with gold though other platable materials can be used such as, for example, Sn/Pb, Cu and the like. The electroplating material fills the via with a central void and also can provide bumps on one or both major surfaces of the substrate, depending upon the amount of plating material used. Plating large amounts of the platable materials results in bumps on the top surface of the wafer whereas plating small amounts of the platable materials results in bumps formed on the bottom surface of the wafer following the gold melting step. The position of the large bump is controlled by the radial extent of the seed material left unetched around the vias and the mass of plating material plated. The radial extent to which the seed layer around the via is left unetched during the resist strip and seed layer etch is controlled (or defined) during the align and expose step. For example, in 10 mil thick substrates with 8 mil diameter vias and a 2 mil wide annular plating material ring around the vias, when the mass of plating material plated is 6 times the amount required to fill a via, large bumps are formed on the top side. When the mass of plating material plated is 5 times the amount required to fill a via, large bumps are formed on the bottom side. Further reduction in the amount of plating material plated makes the bump on the bottom side smaller. The xe2x80x9cbottomxe2x80x9d side or surface is defined herein as that surface on which the plating seed layer is sputtered. This permits the vias and the bumps, if present, to be fabricated during the same operation and thereby eliminates the sequence of operations required in the prior art for fabrication of the bumps. The resist and seed metal are then stripped and the substrate is then placed in a hydrogen-containing ambient, preferably about 10 percent hydrogen and 90 percent nitrogen though the amount of hydrogen can vary from about 5 percent to 100 percent and the other portion of the ambient can be any inert gas, at a temperature above the flow or melting temperature of the plating material and preferably at least 10 degrees C. above the flow or melting temperature of the plating material. This step causes the plating material to flow within the via and to fill the void and drive off any materials which may have been contained in the void. The major surfaces of the substrate are then polished with the plating material extending out of the via being smeared entirely or in part onto one or both major surfaces of the substrate. In this way, the bumps can be retained on one or both major surfaces and, in addition, a ground plane can be provided on a surface or surfaces of the substrate. The substrate is then cleaned to provide the final via-plated substrate.
It follows that, after sufficient plating material is plated within and around the via, the plating metal is then melted in a special ambient to form a solid plug within the via. The interaction between the substrate material and the molten plating material depends upon the plating material melting furnace ambient, the via wall plating material coverage and the mass of plating material plated. The amount of plating material used in the melted via process has been found to be less than used in prior art techniques by a factor of 5. In addition, the labor intensive void cleaning steps are eliminated.
The process modifications discussed below compared to the one discussed earlier improves the hermeticity of the vias. In accordance with a second embodiment of the present invention, the vias are provided through a ceramic substrate, generally but not limited to alumina, preferably by laser drilling. Resist is then formed on the front end of the wafer, the substrate is then properly aligned and the resist is exposed through a mask which patterns the regions of the resist to be exposed. The resist is then exposed through the mask and developed. The diameter of the resist opening around the via is approximately 4 mils larger than the via diameter. A seed metal to which the plating material will be later used will adhere, which includes but is not limited to TiW, Ni, Cr, Ta, Ti and W, is then deposited, preferably by sputtering, over both major opposing surfaces of the substrate which will be connected together by the via to leave seed metal and resist on one major surface and seed metal alone on the other major surface with the via being exposed. When the resist on the front end is removed an annular seed metal ring of width 2 mils is left around all vias. Resist is then deposited on the rear surface of the wafer, the wafer is aligned and the resist is patterned, leaving exposed seed metal around the edges of the via on the major surfaces. The diameter of the resist opening around the via is approximately 4 mils larger than the via diameter. This leaves an annular seed metal ring of width 2 mils is left around all vias. The metal rings around the vias lead to hermetic vias. The substrate is then placed in an electroplating, generally with gold though other platable materials can be used such as, for example, Sn/Pb, Cu and the like. The electroplating material partly fills the via with a pair of somewhat elliptical, preferably non-contacting gold regions which extend above and below the major wafer surfaces. The resist and seed metal are then stripped and the substrate is then placed in a hydrogen-containing ambient, preferably about 10 percent hydrogen and 90 percent nitrogen though the amount of hydrogen can vary from about 5 percent to 100 percent and the other portion of the ambient can be any inert gas, at a temperature above the flow or melting temperature of the plating material and preferably at least 10 degrees C. above the flow or melting temperature of the plating material. This step causes the plating material to flow within the via and to fill the region within the via devoid of gold and drive off any materials which may have been contained in the void. The major surfaces of the substrate are then polished with the plating material extending out of the via being smeared entirely or in part onto one or both major surfaces of the substrate. In this way, the bumps can be retained on one or both major surfaces and, in addition, a ground plane can be provided on a surface or surfaces of the substrate. The substrate is then cleaned to provide the final via-plated substrate. Simple modifications to the above process such as depositing seed layer on both sides of the substrate, coating resist on both surfaces of the substrates and patterning both surfaces of the substrate while leaving an annular seed metal ring of width 2 mils around all vias on both the surfaces also lead to hermetic vias.
It follows with both embodiments that, after sufficient plating material is plated within and around the via, the plating metal is then melted in a special ambient to form a solid plug within the via. The interaction between the substrate material and the molten plating material depends upon the plating material melting furnace ambient, the via wall plating material coverage and the mass of plating material plated. The amount of plating material used in the melted via process has been found to be less than used in prior art techniques by a factor of 5. In addition, the labor intensive void cleaning steps are eliminated.